4位元加法器(另一種行為模式)

module top;
wire [3:0]sum,a,b;
wire c_out,c_in;
system_clock #10 clock1(a[0]);
system_clock #20 clock1(a[1]);
system_clock #40 clock1(a[2]);
system_clock #80 clock1(a[3]);
system_clock #20 clock1(b[0]);
system_clock #30 clock1(b[1]);
system_clock #40 clock1(b[2]);
system_clock #50 clock1(b[3]);
system_clock #60 clock1(c_in);
adder_4_RTL adder_4_RTL1(sum,c_out,a,b,c_in);
endmodule
module adder_4_RTL(sum,c_out,a,b,c_in);
output [3:0]sum;
output c_out;
input [3:0]a,b;
input c_in;
assign{c_out,sum}=a+b+c_in;
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

半加法器

module top;
wire a,b;
wire c_out,sum;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
Add_half myAdd1(sum,c,a,b);
endmodule
module Add_half(Sum,C_out,a,b);
input a,b;
output Sum,C_out;
wire C_out_bar;
xor(Sum,a,b);
nand(C_out_bar,a,b);
not(C_out,C_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

正反器

module top;
wire data_in,clk,rst;
wire q;
system_clock #100 clock1(data_in);
system_clock #50 clock1(clk);
system_clock #1000 clock1(rst);
Filp_flop Filp_flop1(q,data_in,clk,rst);
endmodule
module Filp_flop(q,data_in,clk,rst);
input data_in,clk,rst;
output q;
reg q;
always @(posedge clk)
begin
if(rst==1) q=0;
else q=data_in;
end
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule