正反器

module top;
wire data_in,clk,rst;
wire q;
system_clock #100 clock1(data_in);
system_clock #50 clock1(clk);
system_clock #1000 clock1(rst);
Filp_flop Filp_flop1(q,data_in,clk,rst);
endmodule
module Filp_flop(q,data_in,clk,rst);
input data_in,clk,rst;
output q;
reg q;
always @(posedge clk)
begin
if(rst==1) q=0;
else q=data_in;
end
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule