半加法器

module top;
wire a,b;
wire c_out,sum;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
Add_half myAdd1(sum,c,a,b);
endmodule
module Add_half(Sum,C_out,a,b);
input a,b;
output Sum,C_out;
wire C_out_bar;
xor(Sum,a,b);
nand(C_out_bar,a,b);
not(C_out,C_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule