正位準觸發

module top;
wire enable,data;
wire q_out;
system_clock #200 clock1(enable);
system_clock #100 clock2(data);
latch abc(q_out,enable,data);
endmodule
primitive latch(q_out,enable,data);
output q_out;
input enable,data;
reg q_out;
table
// en data state q_out/next_state
1 1 :?:1;
1 0 :?:0;
0 ? :?:-;
endtable
endprimitive
module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=1;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule

多工器

module top;
wire select,a,b;
wire mux_out;
system_clock #200 clock1(select);
system_clock #100 clock2(a);
system_clock #50 clock3(b);




xxx mux_prim(mux_out,select,a,b);
endmodule
primitive xxx(mux_out,select,a,b);
output mux_out;
input select,a,b;
table
// select a b:mux_out
0 0 0:0;
0 0 1:0;
0 0 x:0;
0 1 0:1;
0 1 1:1;
0 1 x:1;
// select a b:mux_out
1 0 0:0;
1 1 0:0;
1 x 0:0;
1 0 1:1;
1 1 1:1;
1 x 1:1;
x 0 0:0;
x 1 1:1;
endtable
endprimitive






module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=1;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule

很難的 危帳練習

module top;
wire f,c_bar,d,e,f0,f1;
reg a,b,c;
initial
begin
#10 a=1; b=1;
#10 c=1;
#10 c=0;
end
initial
#100 $finish;


AND_gate abs(f0,a,c);
NOT abs1(c_bar,c);
AND_gate abs2(f1,b,c_bar);
or_data ab(f,f0,f1);

AND_gate abs3(f3,a,b);
AND_gate abs(f4,a,c);
AND_gate abs2(f5,b,c_bar);
or_data2 ab1(f2,f3,f4,f5);
endmodule

module AND_gate(c,a,b);
input a,b;
output c;
and(c,a,b);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(a=>c)=(Tpd_0_1,Tpd_1_0);
(b=>c)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module NOT(c_bar,c);
input c;
output c_bar;
wire c;
not(c_bar,c);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(c=>c_bar)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module or_data(f,f0,f1);
input f0,f1;
output f;
wire f;
or(f,f0,f1);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(f0=>f)=(Tpd_0_1,Tpd_1_0);
(f1=>f)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module or_data2(f2,f3,f4,f5);
input f3,f4,f5;
output f2;
wire f2;

or(f2,f3,f4,f5);

specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(f3=>f2)=(Tpd_0_1,Tpd_1_0);
(f4=>f2)=(Tpd_0_1,Tpd_1_0);
(f5=>f2)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=1;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule