多工器

module top;
wire select,a,b;
wire mux_out;
system_clock #200 clock1(select);
system_clock #100 clock2(a);
system_clock #50 clock3(b);




xxx mux_prim(mux_out,select,a,b);
endmodule
primitive xxx(mux_out,select,a,b);
output mux_out;
input select,a,b;
table
// select a b:mux_out
0 0 0:0;
0 0 1:0;
0 0 x:0;
0 1 0:1;
0 1 1:1;
0 1 x:1;
// select a b:mux_out
1 0 0:0;
1 1 0:0;
1 x 0:0;
1 0 1:1;
1 1 1:1;
1 x 1:1;
x 0 0:0;
x 1 1:1;
endtable
endprimitive






module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=1;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule