正位準觸發

module top;
wire enable,data;
wire q_out;
system_clock #200 clock1(enable);
system_clock #100 clock2(data);
latch abc(q_out,enable,data);
endmodule
primitive latch(q_out,enable,data);
output q_out;
input enable,data;
reg q_out;
table
// en data state q_out/next_state
1 1 :?:1;
1 0 :?:0;
0 ? :?:-;
endtable
endprimitive
module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=1;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule