正位準觸發

module top;
wire enable,data;
wire q_out;
system_clock #200 clock1(enable);
system_clock #100 clock2(data);
latch abc(q_out,enable,data);
endmodule
primitive latch(q_out,enable,data);
output q_out;
input enable,data;
reg q_out;
table
// en data state q_out/next_state
1 1 :?:1;
1 0 :?:0;
0 ? :?:-;
endtable
endprimitive
module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=1;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule

多工器

module top;
wire select,a,b;
wire mux_out;
system_clock #200 clock1(select);
system_clock #100 clock2(a);
system_clock #50 clock3(b);




xxx mux_prim(mux_out,select,a,b);
endmodule
primitive xxx(mux_out,select,a,b);
output mux_out;
input select,a,b;
table
// select a b:mux_out
0 0 0:0;
0 0 1:0;
0 0 x:0;
0 1 0:1;
0 1 1:1;
0 1 x:1;
// select a b:mux_out
1 0 0:0;
1 1 0:0;
1 x 0:0;
1 0 1:1;
1 1 1:1;
1 x 1:1;
x 0 0:0;
x 1 1:1;
endtable
endprimitive






module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=1;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule

很難的 危帳練習

module top;
wire f,c_bar,d,e,f0,f1;
reg a,b,c;
initial
begin
#10 a=1; b=1;
#10 c=1;
#10 c=0;
end
initial
#100 $finish;


AND_gate abs(f0,a,c);
NOT abs1(c_bar,c);
AND_gate abs2(f1,b,c_bar);
or_data ab(f,f0,f1);

AND_gate abs3(f3,a,b);
AND_gate abs(f4,a,c);
AND_gate abs2(f5,b,c_bar);
or_data2 ab1(f2,f3,f4,f5);
endmodule

module AND_gate(c,a,b);
input a,b;
output c;
and(c,a,b);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(a=>c)=(Tpd_0_1,Tpd_1_0);
(b=>c)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module NOT(c_bar,c);
input c;
output c_bar;
wire c;
not(c_bar,c);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(c=>c_bar)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module or_data(f,f0,f1);
input f0,f1;
output f;
wire f;
or(f,f0,f1);
specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(f0=>f)=(Tpd_0_1,Tpd_1_0);
(f1=>f)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module or_data2(f2,f3,f4,f5);
input f3,f4,f5;
output f2;
wire f2;

or(f2,f3,f4,f5);

specify
specparam
Tpd_0_1 = 3:3:3,
Tpd_1_0 = 3:3:3;
(f3=>f2)=(Tpd_0_1,Tpd_1_0);
(f4=>f2)=(Tpd_0_1,Tpd_1_0);
(f5=>f2)=(Tpd_0_1,Tpd_1_0);
endspecify
endmodule

module system_clock(clk);
parameter period=100;
output clk;
reg clk;
initial clk=1;
always
begin
#(period/2) clk=~clk;
#(period-period/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)#(period-1)$stop;
endmodule

期中考試

module top;
system_clock #200 clock1(a0);
system_clock #100 clock2(a1);
system_clock #50 clock3(b0);
system_clock #25 clock4(b1);
teacher abs(f,a0,a1,b0,b1);
endmodule
module teacher(f,a0,a1,b0,b1);
input a0,a1,b0,b1;
output f;
wire a0_1,a1_1,b0_1,b1_1,c,d,e,g,h;
not(a0_1,a0);
not(a1_1,a1);
not(b0_1,b0);
not(b1_1,b1);
and(c,a0,b0_1,b1_1);
and(d,a0_1,a1,b1);
and(e,a1,b0,b1);
and(g,a0_1,b0,b1);
and(h,a0_1,a1_1,b0);
or(f,c,d,e,g,h);
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

16位元加法器

延遲圖

4位元加法器(另一種行為模式)

module top;
wire [3:0]sum,a,b;
wire c_out,c_in;
system_clock #10 clock1(a[0]);
system_clock #20 clock1(a[1]);
system_clock #40 clock1(a[2]);
system_clock #80 clock1(a[3]);
system_clock #20 clock1(b[0]);
system_clock #30 clock1(b[1]);
system_clock #40 clock1(b[2]);
system_clock #50 clock1(b[3]);
system_clock #60 clock1(c_in);
adder_4_RTL adder_4_RTL1(sum,c_out,a,b,c_in);
endmodule
module adder_4_RTL(sum,c_out,a,b,c_in);
output [3:0]sum;
output c_out;
input [3:0]a,b;
input c_in;
assign{c_out,sum}=a+b+c_in;
endmodule
module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

半加法器

module top;
wire a,b;
wire c_out,sum;
system_clock #100 clock1(a);
system_clock #50 clock1(b);
Add_half myAdd1(sum,c,a,b);
endmodule
module Add_half(Sum,C_out,a,b);
input a,b;
output Sum,C_out;
wire C_out_bar;
xor(Sum,a,b);
nand(C_out_bar,a,b);
not(C_out,C_out_bar);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

正反器

module top;
wire data_in,clk,rst;
wire q;
system_clock #100 clock1(data_in);
system_clock #50 clock1(clk);
system_clock #1000 clock1(rst);
Filp_flop Filp_flop1(q,data_in,clk,rst);
endmodule
module Filp_flop(q,data_in,clk,rst);
input data_in,clk,rst;
output q;
reg q;
always @(posedge clk)
begin
if(rst==1) q=0;
else q=data_in;
end
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule